1. Field of the Invention
The present invention relates to a ferroelectric memory, more particularly, to a technology for restraining data destruction in a ferroelectric memory due to noise or the like.
2. Description of the Related Art
Conventionally, a memory for storing binary information by utilizing the state of polarization of a ferroelectric capacitor formed on a semiconductor substrate has been known. It is called ferroelectric memory.
FIG. 5 is a graph for illustrating the principle of such a ferroelectric device. In FIG. 5, the vertical axis represents polarization P (μC/cm2) and the horizontal axis represents voltage V (volt). As shown in FIG. 5, the relation between the voltage V and the polarization P exhibits a hysteresis curve H. The inclination of the hysteresis curve H is equivalent to the capacitance [q/V] of the ferroelectric capacitor.
In FIG. 5, it is assumed that the coordinates of an intersection A of the hysteresis curve H and the P-axis in a region of P>0 are (0, p0). Also, a line Cb1 that passes a point B (Vcc, p0) and intersects a line P=p0 at an angle θ is plotted. The angle θ is determined in accordance with the capacitance of a bit line. Moreover, it is assumed that the coordinates of an intersection C the line Cb1 and a reverse response region of the hysteresis curve H are (v1, p1). In this case, the coordinate v1 of the point C coincides with the voltage between the terminals of the ferroelectric capacitor, and the difference v1 (=Vcc−V1) in V-coordinate between the points B and C is the reading voltage (high level) of this ferroelectric device.
In FIG. 5, it is assumed that the coordinates of an intersection D of the hysteresis curve H and the P-axis in a region of P<0 are (0, p2). Also, a line Cb2 that passes a point E (Vcc, p2) and intersects a line P=p2 at the angle θ is plotted. Moreover, it is assumed that the coordinates of an intersection F of the line Cb2 and a non-reverse response region of the hysteresis curve H are (v2, p3). In this case, the coordinate v2 of the point F coincides with the voltage between terminals of the ferroelectric capacitor, and the difference v2 (=Vcc−V2) in V-coordinate between the points E and F is a reading voltage (low level) of this ferroelectric device.
The difference ΔV (=|v1−v2|) in V-coordinate between the points C and F is equivalent to the reading margin of this ferroelectric device. In a 2T2C-type ferroelectric memory (that is, a ferroelectric memory that stores one bit of data by using a pair of ferroelectric capacitors), when ΔV becomes smaller than the discrimination sensitivity of a sense amplifier, the data will have been broken. In a 1T1C-type ferroelectric memory (that is, a ferroelectric memory that stores one bit of data by using one ferroelectric capacitor), when ΔV/2 becomes smaller than the discrimination sensitivity of the sense amplifier, the data will have been broken.
FIG. 6 is a circuit diagram showing the structure of an essential part of a conventional 1T1C-type ferroelectric memory. As shown in FIG. 6, a ferroelectric memory 600 has jxn memory cells MC00 to MCjn for each of memory cell blocks MB0 to MBm. The memory cells of one column in one memory cell block (that is, n memory cells) correspond to one address. The memory cells MC00 to MCjn have one ferroelectric capacitor each, that is, the respective ferroelectric capacitors C00 to Cjn, and one selection transistor each, that is, the respective selection transistors T00 to Tjn. Also, word lines WL0 to WLj and plate lines PL0 to PLj, which are common to the memory cell blocks MB0 to MBm, are arranged in the corresponding rows of the memory cells MC00 to MCjn, respectively. Meanwhile, in each of the memory cell blocks MB0 to MBm, bit lines BL00 to BLmn are provided in the corresponding columns of the memory cells MC00 to MCjn, respectively.
For example, in the case of reading data from the 0-th row (memory cells MC00 to MC0n) of the memory cell block MB0, the word line WL0 and the plate line PL0 are activated by a control circuit (not shown). This turns on the selection transistors T00 to T0n in the 0-th row of each of the memory cell blocks MB0 to MBm, and plate potential is applied to one-side ends of the ferroelectric capacitors C00 to C0n. Thus, in each of the memory cell blocks MB0 to MBm, stored data in the memory cells MC00 to MC0n in the 0-th row are output to the bit lines BL00 to BLmn. The potential of the bit lines BL00 to BLmn is amplified by sense amplifiers SA0 to SAm and sent to a selector circuit 620. The selector circuit 620 selects the bit lines BL00 to BL0n of the memory cell block MB0 from the bit lines BL00 to BLmn and connects the selected bit lines to an n-bit bus 630. Thus, stored data in the 0-th row in the memory cell block MB0 are outputted to outside.
Since the ferroelectric memory performs destructive reading, it is necessary to perform rewriting to all the memory cells from which data is read out. For example, even when data is read out from the 0-th row in the memory cell block MB0 as described above, the data of the 0-th rows in all the memory cell blocks MB0 to MBm are actually read out and therefore, rewriting to all these memory cells blocks MB0 to MBm must be carried out. In rewriting, potential amplified by the sense amplifiers SA0 to SAm is applied again to the bit lines BL00 to BLmn in the state where the word line WL0 and the plate line PL0 have been activated. Thus, the potential of the bit lines BL00 to BLmn is rewritten to the ferroelectric capacitors C00 to C0n in the 0-th row in each of the memory cell blocks MB0 to MBm.
In this manner, in the ferroelectric memory 600 of FIG. 6, every time data of one address is read out, data in the same row must be read out from and rewritten to all the memory cell blocks MB0 to MBm. This is a cause of short device life of the ferroelectric memory 600. Moreover, in the ferroelectric memory 600, since the plate lines PL0 to PLj common to all the memory cell blocks MB0 to MBm are provided, a plate line driver (not shown) having high driving capability is necessary for securing high-speed operation and it causes increase in circuit scale.
On the other hand, FIG. 1 of the following Patent Document 1 discloses a ferroelectric memory having a structure in which plate lines are divided for each memory cell block and in which the divided plate lines can be activated individually. In this ferroelectric memory with such a structure, when reading data of one address, data may be read out from and rewritten to only the memory cells corresponding to that address, and reading from and rewriting to the other memory cell blocks are not necessary. As the frequency of reading from and rewriting to each memory cell can be reduced, the device life becomes longer. Also, since it suffices to activate only one of the divided plate lines, high-speed operation can be secured even when a plate line driver having low driving capability is used.
In the ferroelectric memory described in FIG. 1 of Japanese Patent Application Kokai, No. 10-320981 (hereinafter, referred to as Patent Document 1), all the plate lines corresponding to the memory cells except for selected memory cells (that is, the n memory cells from/to which reading or writing is performed) are in a floating state. However, the plate lines in the floating state are susceptible to the influence of peripheral noise and the influence of signal coupling of the bit lines and the other plate lines. Therefore, at the time of reading from or writing to the selected memory cells, the polarization state of the ferroelectric capacitors in the non-selected memory cells may change. Such change in the polarization state causes change of the reading margin ΔV (see FIG. 5) and destruction of stored data.
Meanwhile, a ferroelectric memory in which plate lines in non-selected rows are grounded to enable prevention of data destruction in the memory cells connected to the plate lines is disclosed in Japanese Patent Application Kokai, No. 2002-184171 (hereinafter, referred to as Patent Document 2). However, with the technique of Patent Document 2, while plate lines in rows that are different from the row of selected memory cells can be grounded, plate lines corresponding to non-selected memory cells in the same row as the selected memory cells cannot be grounded.